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Verilog keyword multi-branch statement example detail

Updated: April 11, 2023 11:52:06 Author: Chasing Dreams towards the Sun
This article mainly introduces the detailed explanation of Verilog keyword multi-branch sentence examples, friends in need can use for reference, I hope to be helpful, I wish you a lot of progress, early promotion and pay rise

Key words: case, selector

The case statement is a form of multiple conditional branches, which can solve the problem of inconvenient use when there are multiple conditional options in the if statement.

case statement

The format of the case statement is as follows:

case(case_expr) condition1 : true_statement1 ; condition2 : true_statement2 ; ... default : default_statement ; endcase

condition1 is executed if Condition1 is true. true_statement1 is executed. If condition1 is false and condition2 is true, then true_statement2 is executed; And so on. If none of the conditions is true, the default_statement statement is executed.

The default statement is optional, and there cannot be more than one default statement in a case statement.

There can be multiple conditional options, not limited to condition1, condition2, etc., and these conditional options are not required to be mutually exclusive. Although these conditional options are compared concurrently, the execution effect is who comes first and who is executed if the condition is true.

Execution statements such as ture_statement1 can be a single statement or multiple statements. If multiple statements are executed, use the begin and end keywords.

case statements support nested use.

The following uses the case statement instead of the if statement to implement a 4-way selector function. The simulation results are in complete agreement with the testbench Reference Conditional Statements chapter.

module mux4to1(
    input [1:0]     sel ,
    input [1:0]     p0 ,
    input [1:0]     p1 ,
    input [1:0]     p2 ,
    input [1:0]     p3 ,
    output [1:0]    sout);
    reg [1:0]     sout_t ;
    always @(*)
        case(sel)
            2'b00:   begin      
                    sout_t = p0 ;
                end
            2'b01:       sout_t = p1 ;
            2'b10:       sout_t = p2 ;
            default:     sout_t = p3 ;
        endcase
    assign sout = sout_t ;
endmodule

Conditional option forms in a case statement need not all be constants, but can also be x or z values.

When the same statement needs to be executed under multiple conditional options, multiple conditional options can be separated by commas and placed in candidates of the same statement block.

However, the comparison logic of x or z in a case statement is not comprehensive, so it is generally not recommended to use x or z as comparison values in a case statement.

For example, extend the case statement for 4-way selectors as follows:

case(sel) 2'b00: sout_t = p0 ; 2'b01: sout_t = p1 ; 2'b10: sout_t = p2 ; 2'b11: sout_t = p3 ; 2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx : sout_t = 2'bxx ; 2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z : sout_t = 2'bzz ; default: $display("Unexpected input control!!!" ); endcase

casex/casez statement

casex and casez statements are variations of case statements to represent irrelevant items in conditional options.

casex uses "x" for irrelevant values, casez uses question marks "?" To represent irrelevant values.

The functions of the two implementations are completely consistent, and the syntax is also completely consistent with the case statement.

However, casex and casez are generally not integrated and are mostly used for simulation.

For example, the casez statement is used to implement a 4-way selector on a 4-bit control terminal.

module mux4to1( input [3:0] sel , input [1:0] p0 , input [1:0] p1 , input [1:0] p2 , input [1:0] p3 , output [1:0] sout); reg [1:0] sout_t ; always @(*) casez(sel) 4'b??? 1: sout_t = p0 ; 4'b?? 1? : sout_t = p1 ; 4'b? 1?? : sout_t = p2 ; 4'b1??? : sout_t = p3 ; default: sout_t = 2'b0 ; endcase assign sout = sout_t ; endmodule

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